1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an array substrate for an IPS mode LCD device and a method for manufacturing the same which are capable of simplifying a manufacturing process.
2. Description of the Related Art
Liquid crystal display (LCD) devices have advantageous features such as low voltage operation, low power consumption, lightweight and slim profile, and full color realization. Because of these advantages, LCD devices are widely used as displays for watches and calculators, as a monitor of a computer, a monitor having television-receiving functions, television sets, and hand-held terminals.
The LCD devices make use of optical anisotropy and polarization properties of liquid crystal because the liquid crystals have a thin and long structure and a directionality to arrange liquid crystal molecules. Therefore, the arrangement direction of the liquid crystal molecules can be controlled by applying an electric field to the liquid crystals. If the arrangement direction of the liquid crystal molecules is arbitrarily adjusted, a polarized light may be arbitrarily modulated based upon the optical anisotropy. In this manner, predetermined images may be displayed on the LCD device.
The TN (Twisted Nematic) mode LCD device is widely used, but has a problem in that the viewing angle is narrow. The technologies for widening such a viewing angle are being studied and include an In Plane Switching (IPS) mode LCD device and a Vertical Alignment (VA) mode LCD device.
FIG. 1 is a schematic plan view showing a portion of a related art IPS mode LCD device. The LCD device includes an array substrate, an opposite substrate arranged opposite the array substrate, and a liquid crystal layer interposed between the array substrate and the opposite substrate.
In FIG. 1, the related art IPS mode LCD device includes a plurality of gate lines 112 spaced apart from each other by a predetermined distance and arranged substantially parallel to a first direction, a plurality of common lines 116 formed in the same direction as the gate lines 112, and a plurality of data lines 124 arranged in a second direction that are substantially perpendicular to the gate lines 112 and the common lines 116. A pixel region P is defined by the gate line 112 and the data line 124.
A thin film transistor T is formed at a crossing point of the gate line 112 and the data line 124. The thin film transistor T includes a gate electrode 114, an active layer (not shown), a source electrode 126 and a drain electrode 128. The source electrode 126 is connected to the data line 124, and the gate electrode 114 is connected to the gate line 112. Also, the drain electrode 128 is connected to the pixel electrode 130.
The pixel electrode 130 includes a plurality of vertical pixel electrode bars 130b and horizontal pixel electrode bars 130a and 130c. The vertical pixel electrode bars 130b are arranged substantially parallel to the data line 124 and spaced apart from one another by a predetermined distance. The horizontal pixel electrode bars 130a and 130c are connected to both ends of the vertical pixel electrode bars 130b and arranged substantially perpendicular to the data line 124. The horizontal pixel electrode bar 130c is connected to the drain electrode 128.
The common electrode 117 is connected to the common line 116. The common electrode 117 includes a plurality of vertical common electrode bars 117b and a horizontal common electrode bar 117a. The vertical common electrode bars 117b are arranged substantially parallel to the data line 124 and spaced apart from the vertical pixel electrode bar 130b by a predetermined distance. The horizontal common electrode bars 117a are connected to the vertical common electrode bars 117b and arranged substantially perpendicular to the data line 124. Each of the vertical common electrode bars 117b has one terminal connected to the common line 116 and the other terminal connected to the horizontal common electrode bar 117a. The horizontal pixel electrode bar 130a is arranged on a portion of the common line 116, with the gate insulating layer (not shown) interposed therebetween. Thus, a storage capacitor C is formed between the common line 116 and the horizontal pixel electrode bar 130a. 
Accordingly, the plurality of vertical pixel electrode bars 130b and the plurality of vertical common electrode 117b are arranged in an alternating pattern and cross each other.
The array substrate for the related art IPS LCD device is generally manufactured using a five-mask process. In other words, the mask process used in the manufacture of the array substrate may include a cleaning, a deposition, a baking, a photo, a development, an etching, a peeling, etc.
A printing process may be used to form an active layer and a contact hole in the array substrate for the related art IPS mode LCD device of FIG. 1. A photo process is used to form the gate electrode, the source/drain electrodes, the channel, the pixel electrode and the common electrode. Generally, the photo process is complex and expensive. On the contrary, the printing process is simple and cheap.
However, the manufacture of the array substrate for the related art IPS mode LCD device requires a large number of mask processes. Also, because three photo processes are required, it costs a great deal and the manufacturing time increases due to the complexity of the process. Therefore, the manufacturing yield may be greatly reduced. When the mask process is reduced by simply one, the manufacturing time, the productivity and the manufacturing cost can be reduced considerably. For these reasons, efforts to reduce the processes have been actively made pursued.